A brief history of RF analog circuit EDA(electronics manufacturing expo news)

02 Aug 2019

Since the introduction of integrated circuits in 1958, the process nodes have grown from 10 microns to 3 nanometers. Among them, advanced semiconductor electronics manufacturing expo manufacturers such as TSMC and Samsung have begun to develop 2nm process. Integrated circuits can be further divided into digital integrated circuits, analog integrated circuits, and digital-to-analog hybrid integrated circuits. Digital integrated circuits and analog integrated circuits present two distinct developments due to differences in design flow and production process.

In recent decades, the integration of digital integrated circuits has become more and more high. In the case of Intel, for example, in 1975, after his founder Gordon Moore published Moore's Law, Intel researchers have always set electronics manufacturing expo goals and targets according to Moore's Law. Under the guidance of Moore's Law, computer integrated circuit chips are getting smaller and smaller, and the computing speed is getting faster and faster.

Moore's Law

In 1971, Intel developed the first commercial processor, the Intel 4004. It integrates 2,300 transistors on-chip, uses a five-layer design, and has a 10-micron process. It can process 4 bits of data and operate 60,000 times per second. After decades of electronics manufacturing expo development, today's processors have reached the 10nm process technology, up to 48 cores, with Intel's latest release of i9-9980HK in 2019 as an example, capable of processing 64-bit data, CPU clock speed up to 5GHz.

Intel 4004

The rapid development of digital integrated circuits has driven the history of automation of EDA tools. EDA (Electronic Design Automation) tools have emerged since the 1960s and until the 1980s, design methods have changed a lot.

CAD (Computer-aided Design) is a technology of the 1970s. It can be called the first generation of EDA tools. Its main functions are interactive graphic editing, design rule checking, and solving transistor-level layout design, PCB layout, and gate-level circuits. Simulation and testing;

In the 1980s, he entered the CAE (Computer-aided Engineering) stage. Due to the gradual expansion of the integrated circuit and the increasing complexity of electronic electronics manufacturing expo systems, people further developed design software and integrated various CAD tools into systems, thereby enhancing circuit function design and Structural design features.

After the 1990s, microelectronics technology has advanced by leaps and bounds. One chip, tens of millions or even hundreds of millions of transistors can be integrated on one chip, which puts higher requirements on EDA technology and promotes the development of EDA technology. Companies have developed large-scale EDA software systems, and EDA technologies characterized by high-level language descriptions, system-level simulations, and comprehensive technologies have emerged.

With the development of technologies such as smart phones, 5G, and Internet of Things in recent years, analog integrated circuits, especially radio frequency integrated circuits, have received more and more attention. However, compared with the rapid electronics manufacturing expo development of digital integrated circuits, the technical progress of analog RF integrated circuits is relatively slow, and the design and design is also very difficult.

Wireless communication system framework

This is mainly due to a large number of parasitic effects, crosstalk and the like in the high frequency circuit. In the process of converting an integrated circuit from a plan paper to an actual circuit, it is necessary to rely strictly on the designer's rich experience. How to layout, how to eliminate various negative effects between components, and compatibility with unsatisfactory components all need to be solved manually by the designer. One of the important reasons for this phenomenon is the lack of good EDA tools as a support.

So, how can design engineers solve these problems without the support of good EDA tools? The usual practice is to leave the design margin large at design time. For example, the two traces that can be close together can be pulled farther, so that the electronics manufacturing expo chip can work, but the chip area is increased; or the frequency reduction is used. The way, for example, the chip that was originally working at 2GHz, down to 1GHz to see if it works, if 1GHz still does not work, then it may work after falling to 500MHz, but the actual working frequency of the chip is only 500MHz, it will lose the chip. performance.

In general, with the rapid development of various electronics manufacturing expo communication systems, the operating frequency of wireless devices continues to increase, and the difficulty of designing high-frequency chips is also increasing.

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