Intel and TSMC's latest 3D packaging technology[electronics manufacturing expo News Flash]

16 Jul 2019

Since April 2018, TSMC has exposed innovative SoIC technology in many technical electronics manufacturing expo forums or seminars. How is this secret weapon that is re-emphasizing Samsung's success?

For the first time, TSMC announced an innovative system-integrated single-chip (SoIC) multi-chip 3D stacking technology at the 24th Annual Technical Symposium in Santa Clara, California, in April 2018.

Advance Moore's Law, Taiwan Semiconductor Power Push SoIC 3D Packaging Technology

As advanced nano-processes are approaching physical electronics manufacturing expo limits, Moore's Law has become unsustainable, and it is no longer possible to reduce linewidth while meeting performance, power, area, and signal transmission speed requirements; coupled with packaging technology that is difficult to keep up with advanced processes. The development process, so Samsung, TSMC, Intel and other foundry giants have stepped into the packaging field, relying on advanced packaging technology to achieve higher performance, lower power consumption, smaller size, faster signal transmission speed.

Even after the gradual entry into the post-Moore's Law era, the development electronics manufacturing expo focus of foundry manufacturers has gradually shifted from the pursuit of more advanced nano-processes to the innovation of packaging technology. However, SoIC was born under such a premise.

If TSMC officially entered the packaging field in 2009, SoIC is a sword that TSMC spent 10 years on, and it is hailed as a high-end packaging technology that can once again take Samsung back to realize 3D IC.

Wafer-to-wafer 3D IC technology

According to TSMC's description of the 24th Annual Technical Symposium, SoIC is an innovative multi-chip stacking technology that is a electronics manufacturing expo wafer-on-wafer bonding technology. This is a 3D IC process technology that allows TSMC to directly produce 3D ICs for customers.

What makes the outside world amazing is that SoIC technology uses TSV technology to achieve a bump-free bonding structure, which can integrate many different adjacent chips, and the most critical and mysterious. The material that is joined is known as a confidential material with a value of up to one billion US dollars. Therefore, it can directly communicate multiple layers of chips through tiny electronics manufacturing expo pores, achieving multiple times more performance in the same volume. In short, it can last. Maintain the advantages of Moore's Law.

It is understood that SoIC is a new generation of innovative packaging technology based on TSMC's CoWoS (Chip on wafer on Substrate) and multi-wafer stack (WoW) packaging technology. It will be applied to wafer-level advanced processes in the future. Bonding technology is seen as a weapon to further strengthen TSMC's advanced nanometer process competitiveness. In October 2018, TSMC gave a clear mass production time for the highly anticipated SoIC technology in the third season of the law conference. It is expected that the revenue contribution of TSMC will be injected in 2020, and it will be mass-produced by 2021, and it will be injected into TSMC. More significant revenue contribution.

In June, when TSMC went to Japan to participate in VLSI technology and circuit seminars to publish technical papers, it also revealed papers on SoIC technology. The paper stated that the SoIC solution stacks bare crystals of different sizes, process technologies and materials. Compared to the traditional three-dimensional integrated circuit solution using electronics manufacturing expo microbumps, TSMC's SoIC has several times higher bump density and speed while significantly reducing power consumption. In addition, SoIC can leverage TSMC's InFO or CoWoS back-end advanced packaging to technology to integrate other chips to create a powerful 3D x 3D system-level solution.

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