September 2026 | Semiconductor Packaging & Advanced Packaging
As AI accelerators, high-performance computing (HPC) and server chips continue to advance, semiconductor packaging is facing increasingly demanding requirements for package size, interconnect density and signal transmission. The competition in advanced packaging is no longer limited to the chip itself. Package substrates, which connect chips to the mainboard, are becoming increasingly critical to performance, power efficiency and signal integrity.
On September 9, Samsung Electro-Mechanics showcased next-generation package substrate technologies at KPCA Show 2026 in Korea, including 2.5D package substrates, 2.1D package substrates and glass substrates. The technologies are part of the company’s efforts to address growing demand for high-value semiconductor packaging driven by AI, servers, data centers and automotive applications.
As AI Computing Demand Grows, Package Substrates Are Becoming a New Bottleneck
The rapid development of generative AI is driving the integration of more high-performance chips and high-bandwidth memory into a single package. As package sizes increase, substrates must accommodate finer circuitry, more interconnections and increasingly complex structures. For large, multilayer package substrates, warpage control, high-speed signal transmission and high-density interconnects are becoming major manufacturing challenges.
Samsung Electro-Mechanics’ 2.5D package substrate technology is designed to address these challenges. The technology focuses on reducing warpage in large, multilayer structures while supporting high-speed signal transmission and high-density chip interconnections. The company also showcased 2.1D package substrates, which use fine circuits and high-density interconnects to enable chip connections without a silicon interposer, offering another potential approach for highly integrated AI semiconductors.
Why Are Glass Substrates Attracting Attention?
Among next-generation packaging materials, glass substrates are emerging as an increasingly important technology direction. Compared with conventional organic substrates, glass offers greater rigidity and dimensional stability, which can help reduce warpage in larger packages and support the industry's move toward higher-density interconnects.
At KPCA Show 2026, Samsung Electro-Mechanics demonstrated glass-based package substrate technologies, including processes for forming micro-scale interconnection channels in glass and filling them with metal, as well as precision surface processing technologies. For AI semiconductors with increasingly large package sizes and complex internal connections, these technologies could help improve package stability and interconnect performance.
However, glass substrates are still undergoing technology development and commercialization. They are not yet replacing conventional organic substrates across the industry. Large-scale adoption will depend on factors including processing technology, yield, cost and compatibility with existing semiconductor manufacturing supply chains.
From 2.5D to Glass Substrates, Advanced Packaging Is Becoming a “Materials + Process” Competition
The technologies showcased by Samsung Electro-Mechanics represent more than a single product upgrade. They reflect a broader shift in semiconductor packaging in the AI era. As chip counts, package sizes and interconnect densities continue to increase, advanced packaging must simultaneously address materials, circuitry, interconnects, thermal management and manufacturing precision.
At the same time, technologies such as 2.5D/3D packaging, Chiplet, HBM and glass substrates are increasingly interconnected as part of the next generation of semiconductor packaging. For the electronics manufacturing ecosystem, this means new opportunities and requirements are emerging across packaging equipment, materials, precision processing, inspection and testing.
NEPCON ASIA 2026: Exploring Next-Generation Semiconductor Packaging & Electronics Manufacturing
From advanced packaging to PCB assembly, the electronics manufacturing industry is moving toward higher integration, greater precision and smarter production. NEPCON ASIA 2026 will bring together the latest technologies and solutions across the electronics manufacturing ecosystem, covering Semiconductor Packaging & Testing, SMT & PCB Assembly, Testing & Inspection, Smart Factory & Automation, Robotics and Machine Vision.
Taking place 27–29 October 2026 at the Shenzhen World Exhibition & Convention Center, China, NEPCON ASIA 2026 will bring together electronics manufacturers, technology providers and industry professionals to explore the next wave of innovation driven by AI, advanced packaging and smart manufacturing.
Date: 27–29 October 2026
Venue: Shenzhen World Exhibition & Convention Center (Bao’an)
Location: Shenzhen, China
Discover the cutting-edge technologies driving the next era of electronics manufacturing at NEPCON ASIA 2026.
Register Now:
NEPCON ASIA 2026 Registration
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NEPCON ASIA 2026 Official Website
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Walden Li
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